<?xml version='1.0' encoding='UTF-8'?><codeBook xmlns="ddi:codebook:2_5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="ddi:codebook:2_5 https://ddialliance.org/Specification/DDI-Codebook/2.5/XMLSchema/codebook.xsd" version="2.5"><docDscr><citation><titlStmt><titl>JART VCM Rth</titl><IDNo agency="DOI">doi:10.26165/JUELICH-DATA/1HWSUA</IDNo></titlStmt><distStmt><distrbtr source="archive">Jülich DATA</distrbtr><distDate>2025-07-15</distDate></distStmt><verStmt source="DVN"><version date="2025-07-15" type="RELEASED">1</version></verStmt><biblCit>Menzel, Stephan; Son, Seokki; Schön, Daniel, 2025, "JART VCM Rth", https://doi.org/10.26165/JUELICH-DATA/1HWSUA, Jülich DATA, V1</biblCit></citation></docDscr><stdyDscr><citation><titlStmt><titl>JART VCM Rth</titl><IDNo agency="DOI">doi:10.26165/JUELICH-DATA/1HWSUA</IDNo></titlStmt><rspStmt><AuthEnty affiliation="Peter Grünberg Institut (PGI-7)">Menzel, Stephan</AuthEnty><AuthEnty affiliation="Peter Grünberg Institut (PGI-7)">Son, Seokki</AuthEnty><AuthEnty affiliation="Peter Grünberg Institut (PGI-7)">Schön, Daniel</AuthEnty></rspStmt><prodStmt/><distStmt><distrbtr source="archive">Jülich DATA</distrbtr><contact affiliation="Peter Grünberg Institut (PGI-7)" email="st.menzel@fz-juelich.de">Menzel, Stephan</contact><depositr>Schön, Daniel</depositr><depDate>2025-07-15</depDate></distStmt></citation><stdyInfo><subject><keyword>Computer and Information Science</keyword><keyword>Engineering</keyword><keyword>Physics</keyword></subject><abstract>This model is an extension of the existing JART (Jülich Aachen Resistive Switching Tools) VCM v1b model, by incorporating state-dependent effective thermal resistance (Rth,eff) based on an electro-thermal continuum model. This enables precise modeling of multilevel behavior and includes the variability in switching cycles to reflect experimental conditions. Figure 1(JART_VCM_Rth_Fig1.jpg) shows that the validation with TaOx-based VCM devices co-integrated with 180 nm n-MOS transistors demonstrates the model’s accuracy, achieving consistent multilevel programming across 7-states and capturing cycle-to-cycle variability effectively. The Verilog-A code of this model and user guide can be downloaded.</abstract><sumDscr/></stdyInfo><method><dataColl><sources/></dataColl><anlyInfo/></method><dataAccs><notes type="DVN:TOU" level="dv">CC0 Waiver</notes><setAvail/><useStmt/></dataAccs><othrStdyMat/></stdyDscr><otherMat ID="f31870" URI="https://data.fz-juelich.de/api/access/datafile/31870" level="datafile"><labl>JART_VCM_Rth_Fig1.jpg</labl><txt>This figure shows that the validation with TaOx-based VCM devices co-integrated with 180 nm n-MOS transistors demonstrates the model’s accuracy, achieving consistent multilevel programming across 7-states and capturing cycle-to-cycle variability effectively.</txt><notes level="file" type="DATAVERSE:CONTENTTYPE" subject="Content/MIME Type">image/jpeg</notes></otherMat><otherMat ID="f31871" URI="https://data.fz-juelich.de/api/access/datafile/31871" level="datafile"><labl>JART VCM Rth veriloga.va</labl><txt>The Verilog-A code of this model</txt><notes level="file" type="DATAVERSE:CONTENTTYPE" subject="Content/MIME Type">application/octet-stream</notes></otherMat></codeBook>