JART VCM v1 genericdoi:10.26165/JUELICH-DATA/QELKG7Jülich DATA2025-03-251Menzel, Stephan; Bengel, Christopher, 2025, "JART VCM v1 generic", https://doi.org/10.26165/JUELICH-DATA/QELKG7, Jülich DATA, V1JART VCM v1 genericdoi:10.26165/JUELICH-DATA/QELKG7Menzel, StephanBengel, ChristopherJülich DATAStephan MenzelComputer and Information ScienceEngineeringPhysicsThe JART VCM v1 generic model is a special variant of the more general JART VCM v1 model. It provides in total 16 data sets to study the influence of the nonlinearity SL of the switching kinetics and the resistance ratio r on different circuit designs [1]. Four different slopes and four different resistance ratios can be chosen. To simplify the comparison, the different slopes intersect at about 1 µs (cf. Figure 1). Thus, the same voltage amplitude and pulse length can be used in a circuit when changing the slope. When increasing the resistance ratio, however, the required switching voltages increases, which is consistent with experimental observations (Fig. 1c, d). To allow for this comparison, the JART VCM v1 model is slightly modified: the electronic transport is assumed to be temperature-independent. The Verilog-A code of this model can be downloaded here (Verilog-A file). The following small errors should be noted: Typos in Table 2 of the paper: Unit of A* should be A/(m2*K2) Nplug should be 25*1026 m-3 Typo in Figure 1 (b) on the x-axis: -1 V and -0.5 V are switched.CC0 Waiverhttps://doi.org/10.1109/ISCAS.2019.8702600[1] A. Siemon, D. J: Wouters, S. Hamdioui and S. Menzel, “Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May, 2019.Figure 1. JART_VCM_v1_generic.jpgFigure 1: (a) Equivalent circuit diagram of the simulation model showing the top electrode (TE), the bottom electrode (BE) and the active oxide layer. (b) Simulated I-V characteristics all resistance ratios r and the nonlinearity SL = 8.83 V-1. (c) Reset and (d) set times vs. applied voltage for all combinations of r and SL. [1].image/jpegVerilog-A JART VCM 1 generic.vaapplication/octet-stream