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Part 1: Document Description
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Citation |
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Title: |
JART VCM Rth |
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Identification Number: |
doi:10.26165/JUELICH-DATA/1HWSUA |
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Distributor: |
Jülich DATA |
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Date of Distribution: |
2025-07-15 |
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Version: |
1 |
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Bibliographic Citation: |
Menzel, Stephan; Son, Seokki; Schön, Daniel, 2025, "JART VCM Rth", https://doi.org/10.26165/JUELICH-DATA/1HWSUA, Jülich DATA, V1 |
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Citation |
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Title: |
JART VCM Rth |
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Identification Number: |
doi:10.26165/JUELICH-DATA/1HWSUA |
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Authoring Entity: |
Menzel, Stephan (Peter Grünberg Institut (PGI-7)) |
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Son, Seokki (Peter Grünberg Institut (PGI-7)) |
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Schön, Daniel (Peter Grünberg Institut (PGI-7)) |
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Distributor: |
Jülich DATA |
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Access Authority: |
Menzel, Stephan |
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Depositor: |
Schön, Daniel |
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Date of Deposit: |
2025-07-15 |
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Study Scope |
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Keywords: |
Computer and Information Science, Engineering, Physics |
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Abstract: |
This model is an extension of the existing JART (Jülich Aachen Resistive Switching Tools) VCM v1b model, by incorporating state-dependent effective thermal resistance (Rth,eff) based on an electro-thermal continuum model. This enables precise modeling of multilevel behavior and includes the variability in switching cycles to reflect experimental conditions. Figure 1(JART_VCM_Rth_Fig1.jpg) shows that the validation with TaOx-based VCM devices co-integrated with 180 nm n-MOS transistors demonstrates the model’s accuracy, achieving consistent multilevel programming across 7-states and capturing cycle-to-cycle variability effectively. The Verilog-A code of this model and user guide can be downloaded. |
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Methodology and Processing |
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Sources Statement |
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Data Access |
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Notes: |
CC0 Waiver |
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Other Study Description Materials |
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Label: |
JART_VCM_Rth_Fig1.jpg |
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Text: |
This figure shows that the validation with TaOx-based VCM devices co-integrated with 180 nm n-MOS transistors demonstrates the model’s accuracy, achieving consistent multilevel programming across 7-states and capturing cycle-to-cycle variability effectively. |
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Notes: |
image/jpeg |
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Label: |
JART VCM Rth veriloga.va |
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Text: |
The Verilog-A code of this model |
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Notes: |
application/octet-stream |