{"@context":"http://schema.org","@type":"Dataset","@id":"https://doi.org/10.26165/JUELICH-DATA/1HWSUA","identifier":"https://doi.org/10.26165/JUELICH-DATA/1HWSUA","name":"JART VCM Rth","creator":[{"name":"Menzel, Stephan","affiliation":"Peter Grünberg Institut (PGI-7)"},{"name":"Son, Seokki","affiliation":"Peter Grünberg Institut (PGI-7)"},{"name":"Schön, Daniel","affiliation":"Peter Grünberg Institut (PGI-7)"}],"author":[{"name":"Menzel, Stephan","affiliation":"Peter Grünberg Institut (PGI-7)"},{"name":"Son, Seokki","affiliation":"Peter Grünberg Institut (PGI-7)"},{"name":"Schön, Daniel","affiliation":"Peter Grünberg Institut (PGI-7)"}],"datePublished":"2025-07-15","dateModified":"2025-07-15","version":"1","description":["This model is an extension of the existing JART (Jülich Aachen Resistive Switching Tools) VCM v1b model, by incorporating state-dependent effective thermal resistance (Rth,eff) based on an electro-thermal continuum model. This enables precise modeling of multilevel behavior and includes the variability in switching cycles to reflect experimental conditions. Figure 1(JART_VCM_Rth_Fig1.jpg) shows that the validation with TaOx-based VCM devices co-integrated with 180 nm n-MOS transistors demonstrates the model’s accuracy, achieving consistent multilevel programming across 7-states and capturing cycle-to-cycle variability effectively. The Verilog-A code of this model and user guide can be downloaded."],"keywords":["Computer and Information Science","Engineering","Physics"],"license":{"@type":"Dataset","text":"CC0","url":"https://creativecommons.org/publicdomain/zero/1.0/"},"includedInDataCatalog":{"@type":"DataCatalog","name":"Jülich DATA","url":"https://data.fz-juelich.de"},"publisher":{"@type":"Organization","name":"Jülich DATA"},"provider":{"@type":"Organization","name":"Jülich DATA"},"distribution":[{"@type":"DataDownload","name":"JART_VCM_Rth_Fig1.jpg","fileFormat":"image/jpeg","contentSize":69745,"description":"This figure shows that the validation with TaOx-based VCM devices co-integrated with 180 nm n-MOS transistors demonstrates the model’s accuracy, achieving consistent multilevel programming across 7-states and capturing cycle-to-cycle variability effectively.","contentUrl":"https://data.fz-juelich.de/api/access/datafile/31870"},{"@type":"DataDownload","name":"JART VCM Rth veriloga.va","fileFormat":"application/octet-stream","contentSize":9594,"description":"The Verilog-A code of this model","contentUrl":"https://data.fz-juelich.de/api/access/datafile/31871"}]}